Digital signal processing is used in a very wide range of applications from high-definition TV, mobile telephony, digital audio, multimedia, digital cameras, radar, sonar detectors, biomedical imaging, global positioning, digital radio, speech recognition, to name a few. Developing both programmable DSP chips and dedicated system-on-chip (SoC) solutions for these applications, has been an active area of research and development over the past three decades. But, the increasing costs of silicon technology have put considerable pressure on developing dedicated SoC solutions. As a remedy to this, recently, the field-programmable gate array (FPGA) has been proposed as a hardware technology for DSP systems as they offer the capability to develop the most suitable circuit architecture for the computational, memory and power requirements of the application in a similar way to SoC systems. Whilst the prefabricated aspect of FPGAs avoids many of the deep submicron problems met when developing system-on-chip (SoC) implementations, the ability to create an efficient implementation from a DSP system description, remains a highly convoluted problem.
As technology has evolved, FPGAs have now become a heterogeneous platform involving multiple hardware and software components and interconnection fabrics. It is clear that there is a strong need for a true system-level design flow, requiring a much higher level system modelling language.